1. Field of the Invention
The present invention relates in general to a semiconductor packaging technique and, more particularly, to a semiconductor chip stack package and a method for manufacturing the semiconductor chip stack package.
2. Description of the Related Art
In an effort to improve integration in a package assembly process, stacking techniques may be employed in which a plurality of integrated circuit (“IC”) chips and/or unit packages may be stacked on a circuit substrate. An example stacking technique may implement bare chip packages.
Bare chip packages (e.g., flip chip packages and wafer level packages) may have IC chips on which conductive bumps may be provided as external connection structures. Bare chip packages may reduce package size to a chip size level, similar to chip scale packages.
Various methods may be employed for manufacturing stack packages using bare chip packages. For example, bare chips may be flip chip bonded on a flexible circuit substrate and the flexible circuit substrate may be bent to form a vertical stack structure. Bare chips may have via holes to connect wirings of upper and lower chips. Bare chips may be mounted on a circuit substrate and connected to the circuit substrate using connection terminals.
Although the conventional methods are generally thought to be acceptable, they are not without shortcomings. For example conventional techniques may result in complicated stack structures and/or conventional techniques may involve difficult and/or inefficient stacking processes. Further, connection terminals connecting upper and lower bare chips may be exposed to the external environment, and this may reduce reliability. The connection terminals (which may be arranged on the outside of bare chips) may lead to increased package size.